Current day data processing systems are designed to maximize speed and optimize performance. A commonly used technique to enhance performance is to increase, within the bounds of technology, the clocking frequency of the system which, in turn, reduces cycle time. However, as the cycle time is shortened, less signal skew can be tolerated since, oftentimes, bits transmitted over busses and the like may be lost or suffer statistical degradation.
Cycle time of high performance data processing systems have been significantly reduced over time, a trend which has been accelerated by the ubiquitous use of multi-cycle path nets at the board and system level. (Multi-cycle path refers to a combinatorial logic path with a delay that exceeds the operating cycle time of the synchronous clocked logic it interfaces).
Multi-cycle paths did not exist some 15 or 20 years ago, when cycle times were longer due to inherently slower circuit delays. Eventually, circuit delay improvements far outpaced those in packaging delay. Indeed, multi-cycle paths today are most evident between packaging levels. They mostly comprise cable busses between boards, and on-board busses between multi-chip modules or cards. As cycle times continue their downward trend and chips increase in density, the composition of a multi-cycle path will eventually shift towards chip-to-chip, and ultimately towards long distances on-chip due to wire delays. These wire delays have less opportunity to improve at the same pace as circuit delays, at which time they will be able to affect cycle time reduction.
Cable net limitations presently determine what constitutes an acceptable range of cycle times which, in turn, define the characteristics of the cable interfaces. Multi-cycle cable interfaces tend to operate over a narrow range of cycle times as a result of signal skewing, a direct consequence of the same clock signals servicing simultaneously very fast and very slow chips. Skews may also be caused by clock variations germane to any clocking signal generator and by variations in physical parameters, such as wire length and via capacitance. Typically, when the limit of a range is reached, boards and other such components having different electrical characteristics must be redesigned or buffered or, alternatively, cables must be substituted to ensure the proper arrival of the clocking signals at the appropriate receiver at the end of a cable net. Practitioners of the art will fully appreciate that proper arrival is not necessarily restricted to signals arriving too late within a cycle but also include signals arriving too early, i.e., prior to a time window opening. The quantification of early and late arrivals will henceforth be referred to as early mode slack and late mode slack, respectively, in contradistinction to the desired average mode slack.
Skewing of signals is also caused in part by the asymmetric nature of a signal, wherein the rise and fall times characteristics differ from each other. This asymmetry reflects itself in the different coefficients used in delay equations which are instrumental in determining the exact switching time of a circuit. The non-symmetrical nature of a rising and a falling pulse affects the early and late mode slacks and plays an important role in timing optimization. It is, therefore, insufficient to just de-skew signals unless a methodology is found to account for the non-symmetrical characteristics of the signals.
Whereas clock skews affect all aspects of hardware design, they are most damaging when they are found in clocking systems. A need exists, though, for handling non-clock nets, particularly, since no correlation exists between clock and non-clock skew minimization. Unlike clock skews which are minimized by modifying appropriate system parameters, bus skew minimization requires more complex handling and solutions.
The design of interfaces between various levels of packaging, namely, between various chips on a module, or modules on a card, etc., and their interconnections, such as wires, cables and the like, have become more critical as machine cycles have shrunk. This is of particular relevance when one considers that multiple cycles of data coexist on these multi-cycle path interconnections while other data bits travel over some other interconnections within the net, forcing the designer to account for these delays in the overall computation of an optimum system operating cycle. For instance, an "n" cycle interface design requires that the minimum delay for the path to be "n-1" cycles, and the maximum delay to be "n" cycles. As "n" increases for the interface, the range of the operable cycle time is reduced.
It is known that busses exist to interface between functional islands. Cycle time can be minimized by setting it according to the shorter path delays between islands. Larger delays associated with communication between one island and the next need to be handled by the aforementioned multi-cycle paths in a synchronous design. Once it is determined that a path does not meet cycle time objectives, it is then designed to ensure that data will be captured by a subsequent synchronous clock pulse. By way of example, if a particular path has a nominal delay of 1.5.times.cycle time, to guarantee capture of the data, one would ensure that the signal will always arrive after one cycle time, and also before two cycle times. Data is placed on the bus and read every cycle, but it takes two cycles for the data to get across. Thus, two cycles worth of data coexist on the bus at any one time (oftentimes, referred to as "storing" data on the bus).
As the cycle time shrinks, the difference between early and late arrivals for the plurality of nets in the multi-cycle cable becomes an ever increasing percentage of the overall cycle time. It therefore reduces the amount wherein the cycle time can vary without experiencing a failure to capture part of the data. Furthermore, since the low operating cycle time variance is inversely proportional to "n", and the high cycle time variation is inversely proportional to "n-1", as "n" increases, the cycle time range correspondingly decreases.
Several solutions for de-skewing and skew compensation have been described. By way of example, Flora et al., in U.S. Pat. Nos. 4,754,164 and 4,755,704 describe a method and an apparatus for automatically de-skewing the clock in a multi-layer circuit board comprised of a plurality of IC chips. On-chip circuitry requiring an accurate delay is provided by means of a strip transmission line formed on the conductive planes of the circuit board.
Another type of solution which has been employed to minimize skew is described by Johnson et al., in U.S. Pat. Nos. 5,077,676 and 5,235,521. of common assignee, wherein the time delay in all clock trees is equalized by equalizing the delay through each level of the tree. This process is achieved by adjusting the capacitance of terminators in each net at each level or by adjusting the power of each driver at each level.
In yet another type of solution described in U.S. Pat. No. 5,258,660 to Nelson et al., the clock delay is precisely adjusted to reduce clock skew by introducing electronically programmable skew adjustment means that incorporates capacitive delay elements that provide multiple signal paths of various delays. These elements are controlled by delay selection circuitry that performs the appropriate delay selection.
All the solutions previously described have the common characteristic of using hardware means for de-skewing clock signals. Practitioners of the art will fully appreciate that hardware solutions suffer a major drawback in that they introduce additional cost, use valuable real estate on the IC chip or package and, oftentimes, require manual adjustments, all of which are expensive and time consuming.
Moreover, present techniques are inadequate in that they do not generally take into account that they require arrival times that differ from bus to bus and from cable to cable. They also fail statistically to maximize the range of acceptable machine cycles for a given cable, board, etc. The absence of multi-cycle path support and the single cycle path support shortcomings dictate the need for a slack based algorithm that will, at the very least, provide a balance between slacks that optimizes the cycle times for designs that encompass multi-cycle paths.